Datasheet

Chapter 5. Debug Support 5-23
Background Debug Mode (BDM)
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt
condition is postponed until the processor core samples for halts/interrupts. The
processor samples for these conditions once during the execution of each
instruction. If there is a pending halt condition at the sample time, the processor
suspends execution and enters the halted state.
The assertion of BKPT
should be considered in the following two special cases:
• After the system reset signal is negated, the processor waits for 16 clock cycles
before beginning reset exception processing. If the BKPT
input is asserted within
eight cycles after RSTI
is negated, the processor enters the halt state, signaling halt
status (0xF) on the PSTDDATA outputs. While the processor is in this state, all
resources accessible through the debug module can be referenced. This is the only
chance to force the processor into emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
GO command depends on
the set of BDM commands performed while it is halted for a breakpoint.
Specifically, if the PC register was loaded, the
GO command causes the processor to
exit halted state and pass control to the instruction address in the PC, bypassing
normal reset exception processing. If the PC was not loaded, the
GO command
causes the processor to exit halted state and continue reset exception processing.
• The ColdFire architecture also handles a special case of BKPT
being asserted while
the processor is stopped by execution of the STOP instruction. For this case, the
processor exits the stopped mode and enters the halted state, at which point, all BDM
commands may be exercised. When restarted, the processor continues by executing
the next sequential instruction, that is, the instruction following the STOP opcode.
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt
conditions. Debug module Revisions A and B clear CSR[27–24] upon a read of the CSR,
but Revision C (in the MCF5407) does not. The debug
GO command clears CSR[26–24].
HALT can be recognized by counting 0xFF occurrences on PSTDDATA. The count is
necessary to determine between a possible data output value of 0xFF and the HALT
condition. Because data always follows a marker (0x8, 0x9, 0xA, or 0xB), PSTDDATA can
display no more than four data 0xFFs. Two such scenarios exist:
• A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF
following:
PSTDDATA[7:0]
0xBF
0xFF
0xFF
0xFF
0xFX (X indicates that the next PST value is guaranteed to not be 0xF)