Datasheet

Chapter 5. Debug Support 5-31

Background Debug Mode (BDM)

5.5.3.3.2 Write A/D Register (WAREG/WDREG)

The operand longword data is written to the speciﬁed address or data register. A write alters

all 32 register bits. A bus error response is returned if the CPU core is not halted.

Command Format:

Command Sequence

Figure 5-23. WAREG/WDREG Command Sequence

Operand Data Longword data is written into the speciﬁed address or data register.

The data is supplied most-signiﬁcant word ﬁrst.

Result Data Command complete status is indicated by returning 0xFFFF (with S

cleared) when the register write is complete.

15 12 11 8 7 4 3 2 0

Command 0x2 0x0 0x8 A/D Register

Result D[31:16]

D[15:0]

Figure 5-22. WAREG/WDREG Command Format

MS DATA

"NOT READY"

XXX

LS DATA

"NOT READY"

NEXT CMD

"NOT READY"

WDREG/WAREG

???

NEXT CMD

"CMD COMPLETE"

BERR