Datasheet

5-42 MCF5407 User’s Manual
Background Debug Mode (BDM)
5.5.3.3.10 Read Control Register (RCREG)
Read the selected control register and return the 32-bit result. Accesses to the
processor/memory control registers are always 32 bits wide, regardless of register width.
The second and third words of the command form a 32-bit address, which the debug
module uses to generate a special bus cycle to access the specified control register. The
12-bit Rc field is the same as that used by the MOVEC instruction.
Command/Result Formats:
Rc encoding:
Command Sequence:
Figure 5-39. RCREG Command Sequence
Operand Data: The only operand is the 32-bit Rc control register select field.
Result Data: Control register contents are returned as a longword,
most-significant word first. The implemented portion of registers
smaller than 32 bits is guaranteed correct; other bits are undefined.
15 12 11 8 7 4 3 0
Command 0x2 0x9 0x8 0x0
0x0 0x0 0x0 0x0
0x0 Rc
Result D[31:16]
D[15:0]
Figure 5-38. RCREG Command/Result Formats
Table 5-23. Control Register Map
Rc Register Definition Rc Register Definition
0x002 Cache control register (CACR) 0x805 MAC mask register (MASK)
0x004 Access control register 0 (ACR0) 0x806 MAC accumulator (ACC)
0x005 Access control register 1 (ACR1) 0x80E Status register (SR)
0x006 Access control register 2 (ACR2) 0x80F Program register (PC)
0x007 Access control register 2 (ACR3) 0xC04 RAM base address register (RAMBAR0)
0x801 Vector base register (VBR) 0xC05 RAM base address register (RAMBAR1)
0x804 MAC status register (MACSR) 0xC0F Memory base address (MBAR)
EXT WORD
"NOT READY"
EXT WORD
"NOT READY"
RCREG
???
NEXT CMD
"NOT READY"
XXX
"NOT READY"
XXX
XXX
BERR
MS RESULT
READ
MEMORY
LOCATION
NEXT CMD
LS RESULT
XXX
MS ADDR
CONTROL
REGISTER
MS ADDR