Datasheet

Chapter 5. Debug Support 5-53
Debug C Definition of PSTDDATA Outputs
Rn represents any {Dn, An} register. In this definition, the ‘y’ suffix generally denotes the
source and ‘x’ denotes the destination operand. For a given instruction, the optional
operand data is displayed only for those effective addresses referencing memory.
Exception Processing
PSTDDATA = C,{B, destination},// stack frame
{B, destination},// stack frame
{B, source},// vector read
PSTDDATA = 5,{[9AB], target}// PC of handler
The PSTDDATA specification for the reset exception is shown below:
Exception Processing
PSTDDATA = C,
PSTDDATA = 5,{[9AB], target}// initial PC
The initial references at address 0 and 4 are never captured nor displayed since these
accesses are treated as instruction fetches.
For all types of exception processing, the PSTDDATA = 0xC value is driven at all times,
unless the PSTDDATA output is needed for one of the optional marker values or for the
taken branch indicator (0x5).
5.8.2 Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the
opcodes shown below. Table 5-28 shows the PSTDDATA specification for these opcodes.
tst.w <ea>x PSTDDATA = 1, {9, source operand}
tst.l <ea>x PSTDDATA = 1, {B, source operand}
unlk Ax PSTDDATA = 1, {B, destination operand}
wddata.b <ea>y PSTDDATA = 4, 8, source operand
wddata.w <ea>y PSTDDATA = 4, 9, source operand
wddata.l <ea>y PSTDDATA = 4, B, source operand
1
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective
address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An),
(d8,An,Xi), (d8,PC,Xi).
2
For move multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the
address reaches a cache line (0-modulo-16) boundary four or more registers are to be transferred. For these
line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.
Automatic line-sized burst transfers maximize performance for these sequential memory accesses.
3
The source operand in predicted RTS is displayed if CSR[12] and/or (CSR[9] or CSR[8]) is set.
4
During normal exception processing, PSTDDATA outputs are driven to 0xC. The exception stack write operands
and the vector read and target address of the exception handler may also be displayed.
Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued)
Instruction Syntax PSTDDATA