Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations xxi
1-1 MCF5407 Block Diagram............................................................................................. 1-2
1-2 UART Module Block Diagram................................................................................... 1-10
1-3 PLL Module................................................................................................................ 1-13
1-4 ColdFire MCF5407 Programming Model .................................................................. 1-15
2-1 ColdFire Enhanced Pipeline ......................................................................................... 2-3
2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-5
2-3 ColdFire Programming Model...................................................................................... 2-8
2-4 Condition Code Register (CCR) ................................................................................... 2-9
2-5 Status Register (SR).................................................................................................... 2-11
2-6 Vector Base Register (VBR)....................................................................................... 2-12
2-7 Organization of Integer Data Formats in Data Registers............................................ 2-13
2-8 Organization of Integer Data Formats in Address Registers ...................................... 2-14
2-9 Memory Operand Addressing..................................................................................... 2-14
2-1 Exception Stack Frame Form...................................................................................... 2-33
3-1 ColdFire MAC Multiplication and Accumulation........................................................ 3-2
3-2 MAC Programming Model........................................................................................... 3-2
4-1 SRAM Base Address Registers (RAMBARn) ............................................................. 4-3
4-2 Data Cache Organization .............................................................................................. 4-7
4-3 Data Cache Organization and Line Format .................................................................. 4-8
4-4 Data Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern............... 4-10
4-5 Data Caching Operation.............................................................................................. 4-11
4-6 Write-Miss in Copyback Mode................................................................................... 4-16
4-7 Data Cache Locking.................................................................................................... 4-20
4-8 Cache Control Register (CACR) ................................................................................ 4-21
4-9 Access Control Register Format (ACRn) ................................................................... 4-24
4-10 An Format (Data Cache)............................................................................................. 4-25
4-11 An Format (Instruction Cache) ................................................................................... 4-25
4-12 Instruction Cache Line State Diagram........................................................................ 4-27
4-13 Data Cache Line State Diagram—Copyback Mode ................................................... 4-28
4-14 Data Cache Line State Diagram—Write-Through Mode ........................................... 4-29
5-1 Processor/Debug Module Interface............................................................................... 5-1
5-2 PSTCLK Timing........................................................................................................... 5-3
5-3 PSTDDATA: Single-Cycle Instruction Timing............................................................ 5-3
5-4 Example JMP Instruction Output on PSTDDATA....................................................... 5-6
5-5 Debug Programming Model ......................................................................................... 5-9
5-6 Address Attribute Trigger Registers (AATR, AATR1).............................................. 5-11