Datasheet

Part II. System Integration Module (SIM) II-i
Part II
System Integration Module (SIM)
Intended Audience
Part II is intended for users who need to understand the interface between the ColdFire core
processor complex, described in Part I, and internal peripheral devices, described in
Part III. It includes a general description of the SIM and individual chapters that describe
components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt
controller for both on-chip and external peripherals, configuration and operation of chip
selects, and the SDRAM controller.
Contents
Part II contains the following chapters:
• Chapter 6, “SIM Overview,” describes the SIM programming model, bus
arbitration, and system-protection functions for the MCF5407.
• Chapter 7, “Phase-Locked Loop (PLL),” describes configuration and operation of
the PLL module. It describes in detail the registers and signals that support the PLL
implementation.
• Chapter 8, “I2C Module,” describes the MCF5407 I2C module, including I2C
protocol, clock synchronization, and the registers in the I2C programing model. It
also provides extensive programming examples.
• Chapter 9, “Interrupt Controller,” describes operation of the interrupt controller
portion of the SIM. Includes descriptions of the registers in the interrupt controller
memory map and the interrupt priority scheme.
• Chapter 10, “Chip-Select Module,” describes the MCF5407 chip-select
implementation, including the operation and programming model, which includes
the chip-select address, mask, and control registers.
• Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,” describes
configuration and operation of the synchronous/asynchronous DRAM controller
component of the SIM. It begins with a general description and brief glossary, and