Datasheet

6-2 MCF5407 User’s Manual
Features
The following is a list of the key SIM features:
• Module base address register (MBAR)
— Base address location of all internal peripherals and SIM resources
— Address space masking to internal peripherals and SIM resources
• Phase-locked loop (PLL) clock control register (PLLCR) for CPU STOP instruction
— Control for turning off clocks to core and interrupt levels that turn clocks back on
Chapter 7, “Phase-Locked Loop (PLL).”
• Interrupt controller
— Programmable interrupt level (1–7) for internal peripheral interrupts
— Programmable priority level (0–3) within each interrupt level
— Four external interrupts; one set to interrupt level 7; three others programmable
to two interrupt levels
See Chapter 9, “Interrupt Controller.”
• Chip select module
— Eight independent, user-programmable chip-select signals (CS
[7:0]) that can
interface with SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
— Address masking for 64-Kbyte to 4-Gbyte memory block sizes
— Programmable wait states and port sizes
— External master access to chip selects
See Chapter 10, “Chip-Select Module.”
• System protection and reset status
— Reset status indicating the cause of last reset
— Software watchdog timer with programmable secondary bus monitor
See Section 6.2.4, “Software Watchdog Timer.”
• Pin assignment register (PAR) configures the parallel port. See Section 6.2.9, “Pin
Assignment Register (PAR).”
• Bus arbitration
— Default bus master park register (MPARK) controls internal and external bus
arbitration and enables display of internal accesses on the external bus for
debugging
— Supports several arbitration algorithms
See Section 6.2.10, “Bus Arbitration Control.”