Datasheet

Chapter 6. SIM Overview 6-11
Programming Model
6.2.10 Bus Arbitration Control
This section describes the bus arbitration register and the four arbitration schemes.
6.2.10.1 Default Bus Master Park Register (MPARK)
The MPARK, shown in Figure 6-9, determines the default bus master arbitration between
internal transfers (core and DMA module) and between internal and external transfers to
internal resources. This arbitration is needed because external masters can access internal
registers within the MCF5407 peripherals.
Figure 6-9. Default Bus Master Register (MPARK)
Table 6-6 describes MPARK bits.
765432 0
Field PARK IARBCTRL EARBCTRL SHOWDATA —
Reset 0000_0000
R/W R/W
Address MBAR + 0x0C
Table 6-6. MPARK Field Descriptions
Bits Name Description
7–6 PARK Park. Indicates the arbitration priority of internal transfers among MCF5407 resources.
00 Round-robin between DMA and ColdFire core
01 Park on master ColdFire core
10 Park on master DMA module
11 Park on current master
Use of this field is described in detail in Section 6.2.10.1.1, “Arbitration for Internally
Generated Transfers (MPARK[PARK]).”
5 IARBCTRL Internal bus arbitration control. Controls external device access to the MCF5407 internal bus.
0 Arbitration disabled (single-master system)
1 Arbitration enabled. IARBCTRL must be set if external masters are using internal
resources like the DRAM controller or chip selects.
Use of this bit depends on whether the system has single or multiple masters, as follows:
• In a single-master system, IARBCTRL should stay cleared, disabling internal arbitration
by external masters. In this scenario, MPARK[PARK] applies only to priority of internal
masters over one another. Note that the internal DMA (master 3) has priority over the
ColdFire core (master 2), if internal DMA bandwidth is at its maximum (BWC = 000).
• In multiple master systems that expect to use internal resources like the DRAM controller
or chip selects, internal arbitration should be enabled. The external master defaults to the
highest priority internal master anytime BG
is negated.
4 EARBCTRL External bus arbitration control. Enables internal register memory space to external bus
arbitration. Internal registers are those accessed at offsets to the MBAR. These include the
SIM, DMA, chip selects, timers, UARTs, I
2
C, and parallel port registers. These registers do
not include the MBAR; only the core can access the MBAR.
0 Arbitration disabled
1 Arbitration enabled
The use of this field is described in detail in Section 6.2.10.1.2, “Arbitration between Internal
and External Masters for Accessing Internal Resources.”