Datasheet

Chapter 7. Phase-Locked Loop (PLL) 7-1
Chapter 7
Phase-Locked Loop (PLL)
This chapter describes configuration and operation of the phase-locked loop (PLL) module.
It describes in detail the registers and signals that support the PLL implementation.
7.1 Overview
The basic features of the MCF5407 PLL implementation are as follows:
• The MCF5407 PLL is enhanced to support faster processor clock (PCLK)
frequencies than the MCF5307. It also offers a wider range of clock input ratios.
• A buffered processor status clock (PSTCLK) is half the PCLK frequency, as
indicated in Figure 7-1. This signal is made available for system development.
The PLL module has the following three modes of operation:
• Reset mode—In reset mode, the core/bus frequency ratio and other configuration
information is sampled. At reset, the PLL asserts the reset out signal, RST
O.
• Normal mode—During normal operations, the divide ratio is programmed at reset
and is clock-multiplied to provide the processor clock frequency. These frequencies
are described in the electrical specifications.”
• Reduced-power mode—In reduced-power mode, the high-speed processor core
clocks are turned off without losing the register contents so that the system can be
reenabled by an unmasked interrupt or reset.
Figure 7-1 shows the frequency relationships of PLL module clock signals.
z
Figure 7-1. PLL Module Block Diagram
PLL
CLKIN
RSTI
Debug Module
DIVIDE[2:0]
RSTO
PCLK (to core)
BCLKO
CLKIN (to on-chip peripherals)
÷2
PSTCLK (= PCLK/2)