Datasheet

Chapter 7. Phase-Locked Loop (PLL) 7-5
Timing Relationships
possible versions of CLKIN/BCLKO. This figure does not show the skew between CLKIN
and PCLK, PSTCLK, and BCLKO. PSTCLK is half the frequency of PCLK. Similarly, the
skew between PCLK and BCLKO is unspecified.
Figure 7-3. CLKIN, PCLK, PSTCLK, and BCLKO Timing
7.4.2 RSTI Timing
Figure 7-4 shows PLL timing during reset. As shown, RSTI must be asserted for at least 16
CLKIN cycles to give the MCF5407 time to begin its initialization sequence. At this time,
the configuration pins should be asserted (D[2:0] for DIVIDE[2:0]), meeting the minimum
setup and hold times to RSTI
given in Chapter 20, “Electrical Specifications.”
On the rising edge of CLKIN before the rising edge of RSTI
, the data on D[7:0] is latched
and the PLL begins ramping to its final operating frequency. During this ramp and lock
time, BCLKO and PSTCLK are held low. The PLL locks in about 2 mS or less depending
on the CLKIN frequency, at which time BCLKO begins normal operation in the specified
mode. The PLL requires 50,000 CLKIN cycles to guarantee PLL lock. To allow for reset
of external peripherals requiring a clock source, RST
O remains asserted for a number of
CLKIN cycles, as shown in Figure 7-4. PSTCLK will begin oscillating a minimum of10
clock cycles after RST
O is negated.
PCLK
CLKIN/ BCLKO (/3)
CLKIN/ BCLKO (/4)
PSTCLK
CLKIN/ BCLKO (/5)
CLKIN/ BCLKO (/6)
NOTE: The clock signals are shown with edges aligned to show frequency relationships only.
Actual signal edges have some skew between them.