Datasheet

Chapter 8. I
2
C Module 8-9
Programming Model
Table 8-5 describes I2SR fields.
8.5.5 I
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C Data I/O Register (I2DR)
In master-receive mode, reading the I2DR, Figure 8-9, allows a read to occur and initiates
76543210
Field ICF IAAS IBB IAL — SRW IIF RXAK
Reset 1000_0001
R/W R R/W
R R/W R
Address MBAR + 0x28C
Figure 8-8. I
2
CR Status Register (I2SR)
Table 8-5. I2SR Field Descriptions
Bits Name Description
7 ICF Data transferring bit. While one byte of data is transferred, ICF is cleared.
0 Transfer in progress
1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
6 IAAS I
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C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check
SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
5 IBB I
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C bus busy bit. Indicates the status of the bus.
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
4 IAL Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by
writing zero to it.)
• SDA sampled low when the master drives high during an address or data-transmit cycle.
• SDA sampled low when the master drives high during the acknowledge bit of a data-receive
cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
3 — Reserved, should be cleared.
2 SRW Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling
address sent from the master. SRW is valid only when a complete transfer has occurred, no other
transfers have been initiated, and the I
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C module is a slave and has an address match.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
1 IIF I
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C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine.
0 No I
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C interrupt pending
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of
the following occurs:
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
0 RXAK Received acknowledge. The value of SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.