Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations xxv
14-5 Modem Control Register (MODCTL) ........................................................................ 14-9
14-6 Tx FIFO Threshold Register (TXLVL) .................................................................... 14-10
14-7 UART Status Register (USRn) ................................................................................. 14-10
14-8 UART Clock-Select Register (UCSRn).................................................................... 14-12
14-9 Receive Samples Available Register (RSMP).......................................................... 14-13
14-10 Tx Space Available Register (TSPC) ....................................................................... 14-13
14-11 UART Command Register (UCRn).......................................................................... 14-14
14-12 UART Receiver Buffer for UART0 (URB0)............................................................ 14-16
14-13 UART Receiver Buffer for UART1 (URB1)............................................................ 14-16
14-14 UART Transmitter Buffer for UART0 (UTB0) ....................................................... 14-16
14-15 UART Transmitter Buffer for UART1 (UTB1) ....................................................... 14-17
14-16 UART Input Port Change Register (UIPCRn).......................................................... 14-17
14-17 UART Auxiliary Control Register (UACRn) ........................................................... 14-18
14-18 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-18
14-19 UART Divider Upper Register (UDUn)................................................................... 14-19
14-20 UART Divider Lower Register (UDLn)................................................................... 14-19
14-21 UART Interrupt Vector Register (UIVRn) ............................................................... 14-20
14-22 UART Input Port Register (UIPn) ............................................................................ 14-20
14-24 UART Block Diagram Showing External and Internal Interface Signals ................ 14-21
14-23 UART Output Port Data 1 Register (UOP1/UOP0) ................................................. 14-21
14-25 UART/RS-232 Interface ........................................................................................... 14-23
14-26 UART1/CODEC Interface........................................................................................ 14-23
14-27 UART1/AC ’97 Interface ......................................................................................... 14-23
14-28 Clocking Source Diagram......................................................................................... 14-24
14-29 Transmitter and Receiver Functional Diagram......................................................... 14-25
14-30 Transmitter Timing Diagram .................................................................................... 14-27
14-31 16-Bit CODEC Interface Timing (lsb First) ............................................................. 14-27
14-32 8-Bit CODEC Interface Timing (msb First) ............................................................. 14-28
14-33 AC ‘97 Interface Timing........................................................................................... 14-28
14-34 Receiver Timing........................................................................................................ 14-30
14-35 Automatic Echo ........................................................................................................ 14-34
14-36 Local Loop-Back ...................................................................................................... 14-34
14-37 Remote Loop-Back ................................................................................................... 14-35
14-38 Multidrop Mode Timing Diagram ............................................................................ 14-36
14-39 UART Mode Programming Flowchart ..................................................................... 14-39
15-1 Parallel Port Pin Assignment Register (PAR) ............................................................ 15-1
15-2 Port A Data Direction Register (PADDR).................................................................. 15-2
15-3 Port A Data Register (PADAT) .................................................................................. 15-3
16-1 Mechanical Diagram................................................................................................... 16-9
16-2 MCF5407 Case Drawing (General View) ................................................................ 16-10
16-3 Case Drawing (Details)............................................................................................. 16-11
17-1 MCF5407 Block Diagram with Signal Interfaces ...................................................... 17-2
17-2 MCF5307 to MCF5407 TM[2:0] Pin Remapping.................................................... 17-18