Datasheet

Chapter 9. Interrupt Controller 9-3
Interrupt Controller Registers
Internal interrupts are programmed to a level and priority. Each internal interrupt has a
unique ICR. Each of the 7 interrupt levels has 5 priorities, for a total of 35 possible priority
levels, encompassing internal and external interrupts. The four external interrupt pins offer
seven possible settings at a fixed interrupt level and priority.
The IRQPAR determines these settings for external interrupt request levels. External
interrupts can be programmed to supply an autovector or execute an external interrupt
acknowledge cycle. This is described in Section 9.2.2, “Autovector Register (AVR).”
9.2.1 Interrupt Control Registers (ICR0–ICR9)
The interrupt control registers (ICR0–ICR9) provide bits for defining the interrupt level and
priority for the interrupt source assigned to the ICR, shown in Table 9-2.
Table 9-3 describes ICR fields.
0x053 ICR7 DMA1
0x054 ICR8 DMA2
0x055 ICR9 DMA3
76543210
Field AVEC — IL IP
Reset 0 — 0_00 00
R/W R/W
Address MBAR + 0x04C (ICR0); 0x04D (ICR1); 0x04E (ICR2); 0x04F (ICR3); 0x050 (ICR4); 0x051 (ICR5);
0x052 (ICR6); 0x053 (ICR7); 0x054 (ICR8); 0x055 (ICR9)
Figure 9-2. Interrupt Control Registers (ICR0–ICR9)
Table 9-3. ICRn Field Descriptions
Bits Field Description
7 AVEC Autovector enable. Determines whether the interrupt-acknowledge cycle input (for the internal
interrupt level indicated in IL for each interrupt) requires an autovector response.
0 Interrupting source returns vector during interrupt-acknowledge cycle.
1 SIM generates autovector during interrupt acknowledge cycle.
6–5 — Reserved, should be cleared.
4–2 IL Interrupt level. Indicates the interrupt level assigned to each interrupt input. See Table 9-4.
1–0 IP Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level
assignment. See Table 9-4.
00 Lowest
01 Low
10 High
11 Highest
Table 9-2. Interrupt Control Registers (Continued)
MBAR Offset Register Name