Datasheet

9-6 MCF5407 User’s Manual
Interrupt Controller Registers
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Table 9-6 shows the correlation between AVR[AVEC] and the external interrupts. Note that
an AVECn bit is valid only when the corresponding external interrupt request level is
enabled in the IRQPAR.
9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)
The interrupt pending register (IPR), Figure 9-4, makes visible the interrupt sources that
have an interrupt pending. The interrupt mask register (IMR), also shown in Figure 9-4, is
used to mask the internal and external interrupt sources.
NOTE:
To mask interrupt sources, first set the core’s status register
interrupt mask level to that of the source being masked in the
IMR. Then, the IMR bit can be masked.
An interrupt is masked by setting, and enabled by clearing, the corresponding IMR bit.
When a masked interrupt occurs, the corresponding IPR bit is still set, but no interrupt
request is passed to the core.
Table 9-5. AVR Field Descriptions
Bit Name Description
7–1 AVEC Autovector control. Determines whether the external interrupt at that level is autovectored.
0 Interrupting source returns vector during interrupt-acknowledge cycle.
1 SIM generates autovector during interrupt-acknowledge cycle.
0 BLK Block address strobe (AS
) for external AVEC access. Available for users who use AS as a global
chip select for peripherals and do not want to enable them during an AVEC cycle.
0 Do not block address strobe.
1 Block address strobe from asserting.
Table 9-6. Autovector Register Bit Assignments
Autovector Interrupt Source Autovector Register Bit Location Vector Offset
External interrupt request 1 AVEC1 0x64
External interrupt request 2 AVEC2 0x68
External interrupt request 3 AVEC3 0x6C
External interrupt request 4 AVEC4 0x70
External interrupt request 5 AVEC5 0x74
External interrupt request 6 AVEC6 0x78
External interrupt request 7 AVEC7 0x7C