Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
xxvi MCF5407 User’s Manual
18-1 Signal Relationship to CLKIN for Non-DRAM Access............................................. 18-2
18-2 Connections for External Memory Port Sizes ............................................................ 18-4
18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4
18-4 Data Transfer State Transition Diagram ..................................................................... 18-6
18-5 Read Cycle Flowchart................................................................................................. 18-7
18-6 Basic Read Bus Cycle................................................................................................. 18-8
18-7 Write Cycle Flowchart................................................................................................ 18-9
18-8 Basic Write Bus Cycle ................................................................................................ 18-9
18-9 Read Cycle with Fast Termination ........................................................................... 18-10
18-10 Write Cycle with Fast Termination........................................................................... 18-10
18-11 Back-to-Back Bus Cycles ......................................................................................... 18-11
18-12 Line Read Burst (2-1-1-1), External Termination .................................................... 18-12
18-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13
18-14 Line Read Burst (3-2-2-2), External Termination .................................................... 18-13
18-15 Line Read Burst-Inhibited, Fast, External Termination............................................ 18-14
18-16 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 18-14
18-17 Line Write Burst (3-2-2-2) with One Wait State, Internal Termination ................... 18-15
18-18 Line Write Burst-Inhibited, Internal Termination .................................................... 18-15
18-19 Longword Read from an 8-Bit Port, External Termination...................................... 18-16
18-20 Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16
18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17
18-22 Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17
18-23 Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20
18-24 Basic No-Wait-State External Master Access .......................................................... 18-22
18-25 External Master Burst Line Access to 32-Bit Port.................................................... 18-24
18-26 MCF5407 Two-Wire Mode Bus Arbitration Interface............................................. 18-25
18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26
18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27
18-29 MCF5407 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28
18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30
18-31 Three-Wire Bus Arbitration...................................................................................... 18-31
18-32 Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32
18-33 Master Reset Timing................................................................................................. 18-34
18-34 Software Watchdog Reset Timing ............................................................................ 18-35
19-1 JTAG Test Logic Block Diagram ............................................................................... 19-2
19-2 JTAG TAP Controller State Machine......................................................................... 19-4
19-3 IDCODE Register ....................................................................................................... 19-6
19-4 Disabling JTAG in JTAG Mode ............................................................................... 19-11
19-5 Disabling JTAG in Debug Mode .............................................................................. 19-11
20-1 Supply Voltage Sequencing and Separation Cautions................................................ 20-3
20-2 Example Circuit to Control Supply Sequencing......................................................... 20-4
20-3 CLKIN-to-Core Clock Frequency Ranges.................................................................. 20-4
20-4 Clock Timing .............................................................................................................. 20-5