Datasheet

10-2 MCF5407 User’s Manual
Chip-Select Operation
10.3 Chip-Select Operation
Each chip select has a dedicated set of the following registers for configuration and control.
• Chip-select address registers (CSARn) control the base address space of the chip
select. See Section 10.4.1.1, “Chip-Select Address Registers (CSAR0–CSAR7).”
Table 10-2. Byte Enables/Byte Write Enable Signal Settings
Transfer Size Port Size A1 A0
BE0/BWE0 BE1/BWE1 BE2/BWE2 BE3/BWE3
D[31:24] D[23:16] D[15:8] D[7:0]
Byte 8-bit 0 0 0111
010111
100111
110111
16-bit 0 0 0 1 1 1
011011
100111
111011
32-bit 0 0 0 1 1 1
011011
101101
111110
Word 8-bit 0 0 0 1 1 1
010111
100111
110111
16-bit 0 0 0 0 1 1
100011
32-bit 0 0 0 0 1 1
101100
Longword 8-bit 0 0 0111
010111
100111
110111
16-bit 0 0 0 0 1 1
100011
32-bit 0 0 0 0 0 0
Line 8-bit 0 0 0111
010111
100111
110111
16-bit 0 0 0 0 1 1
100011
32-bit 0 0 0 0 0 0