Datasheet

Chapter 10. Chip-Select Module 10-3
Chip-Select Operation
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access
control. See Section 10.4.1.2, “Chip-Select Mask Registers (CSMR0–CSMR7).”
• Chip-select control registers (CSCRn) provide port size and burst capability
indication, wait-state generation, and automatic acknowledge generation features.
See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).”
Each CS
n can assert during specific CPU space accesses such as interrupt-acknowledge
cycles and each can be accessed by an external master. CS0
is a global chip select after reset
and provides relocatable boot ROM capability.
10.3.1 General Chip-Select Operation
When a bus cycle is initiated, the MCF5407 first compares its address with the base address
and mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7)
and DRAM block 0 and 1 address and control registers (configured in DACR0 and
DACR1). If the driven address matches a programmed chip select or DRAM block, the
appropriate chip select is asserted or the DRAM block is selected using the specifications
programmed in the respective configuration register. Otherwise, the following occurs:
• If the address and attributes do not match in CSCR or DACR, the MCF5407 runs an
external burst-inhibited bus cycle with a default of external termination on a 32-bit
port.
• Should an address and attribute match in multiple CSCRs, the matching chip-select
signals are driven; however, the MCF5407 runs an external burst-inhibited bus cycle
with external termination on a 32-bit port.
• Should an address and attribute match both DACRs or a DACR and a CSCR, the
operation is undefined.
Table 10-3 shows the type of access as a function of match in the CSCRs and DACRs.
Table 10-3. Accesses by Matches in CSCRs and DACRs
Number of CSCR Matches Number of DACR Matches Type of Access
0 0 External
10 Defined by CSCR
Multiple 0 External, burst-inhibited, 32-bit
01 Defined by DACRs
1 1 Undefined
Multiple 1 Undefined
0 Multiple Undefined
1 Multiple Undefined
Multiple Multiple Undefined