Datasheet

Chapter 10. Chip-Select Module 10-7
Chip-Select Registers
10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)
The chip select mask registers, Figure 10-3, are used to specify the address mask and
allowable access types for the respective chip selects.
.
Table 10-9 describes CSMR fields.
Table 10-8. CSARn Field Description
Bits Name Description
15–0 BA Base address. Defines the base address for memory dedicated to chip select CS
[7:0]. BA is compared
to bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.
31 1615 9876543210
Field BAM — WP — AM C/I SC SD UC UD V
Reset Unitialized 0
R/W R/W
Addr 0x084 (CSMR0); 0x090 (CSMR1); 0x09C (CSMR2); 0x0A8 (CSMR3);
0x0B4 (CSMR4); 0x0C0 (CSMR5); 0x0CC (CSMR6); 0x0D8 (CSMR7)
Figure 10-3. Chip Select Mask Registers (CSMRn)
Table 10-9. CSMRn Field Descriptions
Bits Name Description
31–16 BAM Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit
causes the corresponding CSAR bit to be ignored in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for CS
[7:0] is 2
n
; n = (number of bits set in respective CSMR[BAM]) + 16.
So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008, CS0
would address two discontinuous
64-Kbyte memory blocks: one from 0x0000–0xFFFF and one from 0x8_0000–0x8_FFFF.
Likewise, for CS0
to access 32 Mbytes of address space starting at location 0x0, CS1 must begin
at the next byte after CS0
for a 16-Mbyte address space. Then CSAR0 = 0x0000,
CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] = 0x00FF.
8 WP Write protect. Controls write accesses to the address range in the corresponding CSAR.
Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate
chip select not being selected. No exception occurs.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed.
7 — Reserved, should be cleared.
6 AM Alternate master. When AM = 0 during an external master or DMA access, SC, SD, UC, and UD
are don’t cares in the chip-select decode.