Datasheet

10-8 MCF5407 User’s Manual
Chip-Select Registers
10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7)
Each chip-select control register, Figure 10-4, controls the auto acknowledge, external
master support, port size, burst capability, and activation of each chip select. Note that to
support the global chip select, CS0
, the CSCR0 reset values differ from the other CSCRs.
CS0
allows address decoding for boot ROM before system initialization.
Figure 10-4. Chip-Select Control Registers (CSCR0–CSCR7)
Table 10-10 describes CSCRn fields.
5–1 C/I,
SC,
SD,
UC,
UD
Address space mask bits. These bits determine whether the specified accesses can occur to the
address space defined by the BAM for this chip select.
C/I CPU space and interrupt acknowledge cycle mask
SC Supervisor code address space mask
SD Supervisor data address space mask
UC User code address space mask
UD User data address space mask
0 The address space assigned to this chip select. is available to the specified access type.
1 The address space assigned to this chip select. is not available (masked) to the specified access
type. If this address space is accessed, chip select is not activated and a regular external bus
cycle occurs.
Note that if if AM = 0, SC, SD, UC, and UD are ignored in the chip select decode on external
master or DMA access.
0 V Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid.
Programmed chip selects do not assert until V is set (except for CS0
, which acts as the global chip
select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
151413 1098765 4 3 2 0
Field — WS — AA PS1 PS0 BEM BSTR BSTW —
Reset: CSCR0 — 11_11 — D7 D6 D5 D3 —
Reset: Other CSCRs Unitialized
R/W R/W
Address 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3);
0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6); 0x0DE (CSCR7)
Table 10-10. CSCRn Field Descriptions
Bits Name Description
15–14 — Reserved, should be cleared.
13–10 WS Wait states. The number of wait states inserted before an internal transfer acknowledge is generated
(WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, T
A must be asserted by
the external system regardless of the number of wait states generated. In that case, the external
transfer acknowledge ends the cycle. An external T
A supersedes the generation of an internal TA.
9 — Reserved, should be cleared.
Table 10-9. CSMRn Field Descriptions (Continued)
Bits Name Description