Datasheet

Chapter 10. Chip-Select Module 10-9
Chip-Select Registers
10.4.1.4 Code Example
The code below provides an example of how to initialize the chip-selects. Only chip selects
0, 1, 2, and 3 are programmed here; chip selects 4, 5, 6, and 7 are left invalid. MBARx
defines the base of the module address space.
CSAR0 EQU MBARx+0x080 ;Chip select 0 address register
CSMR0 EQU MBARx+0x084 ;Chip select 0 mask register
CSCR0 EQU MBARx+0x08A ;Chip select 0 control register
CSAR1 EQU MBARx+0x08C ;Chip select 1 address register
CSMR1 EQU MBARx+0x090 ;Chip select 1 mask register
CSCR1 EQU MBARx+0x096 ;Chip select 1 control register
CSAR2 EQU MBARx+0x098 ;Chip select 2 address register
CSMR2 EQU MBARx+0x09C ;Chip select 2 mask register
CSCR2 EQU MBARx+0x0A2 ;Chip select 2 control register
CSAR3 EQU MBARx+0x0A4 ;Chip select 3 address register
CSMR3 EQU MBARx+0x0A8 ;Chip select 3 mask register
CSCR3 EQU MBARx+0x0AE ;Chip select 3 control register
CSAR4 EQU MBARx+0x0B0 ;Chip select 4 address register
CSAR4 EQU MBARx+0x0B4 ;Chip select 4 mask register
CSMR4 EQU MBARx+0x0BA ;Chip select 4 control register
8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for
accesses specified by the chip-select address.
0 No internal T
A is asserted. Cycle is terminated externally.
1 Internal T
A is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the
external system asserts an external T
A before the wait-state countdown asserts the internal TA, the
cycle is terminated. Burst cycles increment the address bus between each internal termination.
7–6 PS Port size. Specifies the width of the data associated with each chip select. It determines where data
is driven during write cycles and where data is sampled during read cycles. See Section 10.3.1.1,
“8-, 16-, and 32-Bit Port Sizing.”
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5 BEM Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must
be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the
appropriate mode of byte enable in support of these SRAMs.
0 Neither BE
nor BWE is asserted for read. BWE is generated for data write only.
1BE
is asserted for read; BWE is asserted for write.
4 BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each CS
n.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and
16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
3 BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CS
n.
0 Break data larger than the specified port size into individual port-sized, non-burst writes. For
example, a longword write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and
16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports.
2–0 — Reserved, should be cleared.
Table 10-10. CSCRn Field Descriptions
Bits Name Description