Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-1
Chapter 11
Synchronous/Asynchronous DRAM
Controller Module
This chapter describes configuration and operation of the synchronous/asynchronous
DRAM controller component of the system integration module (SIM). It begins with a
general description and brief glossary, and includes a description of signals involved in
DRAM operations. The remainder of the chapter consists of the two following parts:
• Section 11.3, “Asynchronous Operation,” describes the programming model and
signal timing for the four basic asynchronous modes.
— Non-page mode
— Burst page mode
— Continuous page mode
— Extended data-out mode
• Section 11.4, “Synchronous Operation,” describes the programming model and
signal timing, as well as the command set required for synchronous operations. This
section also includes extensive examples the designer can follow to better
understand how to configure the DRAM controller for synchronous operations.
11.1 Overview
The DRAM controller module provides glueless integration of DRAM with the ColdFire
product. The key features of the DRAM controller include the following:
• Support for two independent blocks of DRAM
• Interface to standard synchronous/asynchronous dynamic random access memory
(ADRAM/SDRAM) components
• Programmable SRAS
, SCAS, and refresh timing
• Support for page mode
• Support for 8-, 16-, and 32-bit wide DRAM blocks
• Support for synchronous and asynchronous DRAMs, including EDO DRAM,
SDRAM, and fast page mode