Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations xxvii
20-5 PSTCLK Timing......................................................................................................... 20-6
20-6 AC Timings—Normal Read and Write Bus Cycles ................................................... 20-8
20-7 SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN ............................... 20-9
20-8 SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN ............................ 20-10
20-9 SDRAM Read Cycle with EDGESEL Tied High..................................................... 20-11
20-10 SDRAM Write Cycle with EDGESEL Tied High.................................................... 20-12
20-11 SDRAM Read Cycle with EDGESEL Tied Low ..................................................... 20-13
20-12 SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-14
20-13 AC Output Timing—High Impedance...................................................................... 20-14
20-14 Reset Timing............................................................................................................. 20-15
20-15 Real-Time Trace AC Timing .................................................................................... 20-16
20-16 BDM Serial Port AC Timing .................................................................................... 20-16
20-17 Timer Module AC Timing........................................................................................ 20-17
20-18 I
2
C Input/Output Timings......................................................................................... 20-19
20-19 UART0 and UART1 Module AC Timing—UART Mode ....................................... 20-20
20-20 UART1 in 8- and 16-bit CODEC Mode ................................................................... 20-21
20-21 UART1 in AC ‘97 Mode .......................................................................................... 20-21
20-22 General-Purpose I/O Timing..................................................................................... 20-22
20-23 DMA Timing ............................................................................................................ 20-23
20-24 IEEE 1149.1 (JTAG) AC Timing ............................................................................. 20-25
A-1 MCF5307 to MCF5407 TM[2:0] Pin Remapping....................................................... A-5
A-2 Simplified Block Diagram ........................................................................................... A-6
A-3 PLL Module................................................................................................................. A-7
A-4 Exception Stack Frame Form .................................................................................... A-11
A-5 Write Debug Module Register Command (
WDMREG)............................................... A-12
A-6
WDMREG Command Sequence................................................................................... A-13
A-7 PLL Power Supply Filter Circuit............................................................................... A-18