Datasheet

11-2 MCF5407 User’s Manual
Overview
11.1.1 Defi nitions
The following terminology is used in this chapter:
• A/SDRAM block—Any group of DRAM memories selected by one of the
MCF5407 RAS
[1:0] signals. Thus, the MCF5407 can support two independent
memory blocks. The base address of each block is programmed in the DRAM
address and control registers (DACR0 and DACR1).
• SDRAM—RAMs that operate like asynchronous DRAMs but with a synchronous
clock, a pipelined, multiple-bank architecture, and faster speed.
• SDRAM bank—An internal partition in an SDRAM device. For example, a 64-Mbit
SDRAM component might be configured as four 512K x 32 banks. Banks are
selected through the SDRAM component’s bank select lines.
11.1.2 Block Diagram and Major Components
The basic components of the DRAM controller are shown in Figure 11-1.
Figure 11-1. Asynchronous/Synchronous DRAM Controller Block Diagram
The DRAM controller’s major components, shown in Figure 11-1, are described as
follows:
• DRAM address and control registers (DACR0 and DACR1)—The DRAM
controller consists of two configuration register units, one for each supported
memory block. DACR0 is accessed at MBAR + 0x0108; DACR1 is accessed at
0x010. The register information is passed on to the hit logic.
Memory Block 0 Hit Logic
DRAM Address/Control Register 0
(DACR0)
A[31:0]
Internal
Address
Control Logic
and
RAS[1:0]
CAS
[3:0]
DRAMW
DRAM Controller Module
Refresh Counter
SCAS
SRAS
SCKE
State Machine
Multiplexing
Page Hit
Logic
DRAM Control
Register (DCR)
Bus
Memory Block 1 Hit Logic
DRAM Address/Control Register 1
(DACR1)
These signals
A[31:0]
are used for
SDRAM only