Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-3
DRAM Controller Operation
• Control logic and state machine—Generates all DRAM signals, taking bus cycle
characteristic data from the block logic, along with hit information to generate
DRAM accesses. Handles refresh requests from the refresh counter.
— DRAM control register (DCR)—Contains data to control refresh operation of
the DRAM controller. Both memory blocks are refreshed concurrently as
controlled by DCR[RC].
— Refresh counter—Determines when refresh should occur, determined by the
value of DCR[RC]. It generates a refresh request to the control block.
• Hit logic—Compares address and attribute signals of a current DRAM bus cycle to
both DACRs to determine if a DRAM block is being accessed. Hits are passed to the
control logic along with characteristics of the bus cycle to be generated.
• Page hit logic—Determines if the next DRAM access is in the same DRAM page as
the previous one. This information is passed on to the control logic.
• Address multiplexing—Multiplexes addresses to allow column and row addresses
to share pins. This allows glueless interface to DRAMs.
11.2 DRAM Controller Operation
The DRAM controller mode is programmed through DCR[SO]. Asynchronous mode
(SO = 0) includes support for page mode and EDO DRAMs. Synchronous mode is
designed to work with industry-standard SDRAMs. These modes act very differently from
one another, especially regarding the use of DRAM registers and pins. Memory blocks
cannot operate in different modes; both are either synchronous or asynchronous.
11.2.1 DRAM Controller Registers
The DRAM controller registers memory map, Table 11-1, is the same regardless of whether
asynchronous or synchronous DRAM is used, although bit configurations may vary.
NOTE:
External masters cannot access MCF5407 on-chip memories or
MBAR, but they can access DRAM controller registers.
Table 11-1. DRAM Controller Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x100 DRAM control register (DCR) [p. 11-4] Reserved
0x104 Reserved
0x108 DRAM address and control register 0 (DACR0) [p. 11-5]
0x10C DRAM mask register block 0 (DMR0) [p. 11-7]
0x110 DRAM address and control register 1 (DACR1) [p. 11-5]
0x114 DRAM mask register block 1 (DMR1) [p. 11-7]