Datasheet

11-8 MCF5407 User’s Manual
Asynchronous Operation
11.3.3 General Asynchronous Operation Guidelines
The DRAM controller provides control for RAS, CAS, and DRAMW signals, as well as
address multiplexing and bus cycle termination. Whether the mode is synchronous or
asynchronous determines signal control and termination. To reduce complexity,
multiplexing is the same for both modes. Table 11-6 shows the scheme for DRAM
configurations. This scheme works for symmetric configurations (in which the number of
rows equals the number of columns) as well as asymmetric configurations (in which the
number of rows and columns are different).
6–1AMx Address modifier masks. Determine which accesses can occur in a given DRAM block.
0 Allow access type to hit in DRAM
1 Do not allow access type to hit in DRAM
Bit Associated Access Type Access Definition
C/I CPU space/interrupt acknowledge MOVEC instruction or interrupt acknowledge cycle
AM Alternate master External or DMA master
SC Supervisor code Any supervisor-only instruction access
SD Supervisor data Any data fetched during the instruction access
UC User code Any user instruction
UD User data Any user data
0 V Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded.
0 Do not decode DRAM accesses.
1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded.
Table 11-6. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address Notes Relating to Port Sizes
17 17 0 8-bit port only
16 16 1 8- and 16-bit ports only
15 15 2
14 14 3
13 13 4
12 12 5
11 11 6
10 10 7
99 8
17 17 16 32-bit port only
18 18 17 16-bit port only or 32-bit port with only 8 column address lines
19 19 18 16-bit port only when at least 9 column address lines are used
Table 11-5. DMR0/DMR1 Field Descriptions (Continued)
Bits Name Description