Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-11
Asynchronous Operation
11.3.3.1 Non-Page-Mode Operation
In non-page mode, the simplest mode, the DRAM controller provides termination and runs
a separate bus cycle for each data transfer. Figure 11-5 shows a non-page-mode access in
which a DRAM read is followed by a write. Addresses for a new bus cycle are driven at the
rising clock edge.
For a DRAM block hit, the associated RAS
is driven at the next falling edge. Here
DACRn[RCD] = 0, so the address is multiplexed at the next rising edge to provide the
column address. The required CAS
signals are then driven at the next falling edge and
remain asserted for the period programmed in DACRn[CAS]. Here, DACRn[RNCN] = 1,
so it is precharged one clock before CAS
is negated. On a read, data is sampled on the last
rising edge of the clock that CAS
is valid.
Figure 11-5. Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4)
Table 11-9. DRAM Addressing for 32-Bit Wide Memories
MCF5407 Address
Pin
MCF5407 Address Bit
Driven for RAS
MCF5407 Address Bit Driven
when CAS is Asserted
Memory Size
15 15 2
Base Memory Size of
64 Kbytes
14 14 3
13 13 4
12 12 5
11 11 6
10 10 7
99 8
17 17 16 256 Kbytes
19 19 18 1 Mbyte
21 21 20 4 Mbytes
23 23 22 16 Mbytes
25 25 24 64 Mbytes
A[31:0]
RAS[1] or [0]
CAS[3:0]
DRAMW
D[31:0]
DACRn[RCD] = 0 DACRn[RNCN] = 1
DACRn[CAS] = 01]
Row Column
CLKIN