Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-13
Asynchronous Operation
Figure 11-7. Burst Page-Mode Read Operation (4-3-3-3)
Figure 11-8 shows the write operation with the same configuration.
Figure 11-8. Burst Page-Mode Write Operation (4-3-3-3)
11.3.3.3 Continuous Page Mode
Continuous page mode (DACRn[PM] = 11) is a type of page mode that balances
performance, complexity, and size. In typical page-mode implementations, sequential
addresses are checked for multiple hits in a DRAM block. On a hit, RAS
remains asserted
and CAS
is asserted with the new column address. On a miss, RAS must be precharged
again before the bus cycle begins.
Continuous page mode supports page-mode operation without requiring an address holding
register per memory block and eliminates the delay for a miss-to-precharge RAS
for the
upcoming bus cycle. Because the internal MCF5407 address bus is pipelined, addresses for
A[31:0]
RAS[1] or [0]
CAS[3:0]
DRAMW
D[31:0]
RCD = 0
CAS = 01
Row ColumnColumn Column Column
CLKIN
A[31:0]
RAS
[1] or [0]
CAS[3:0]
DRAMW
D[31:0]
RCD = 0
CAS = 01
Row ColumnColumn Column Column
CLKIN