Datasheet

11-14 MCF5407 User’s Manual
Asynchronous Operation
the next bus cycle are often available before the current cycle completes. The two addresses
are compared at the end of the cycle to determine if the next address hits the same page. If
so, RAS
remains asserted. If not, or if no access is pending, RAS is precharged before the
next bus cycle is active on the external bus. As a result, a page miss suffers no penalty.
Single accesses not followed by a hit in the page look like non-page-mode accesses.
Figure 11-9 shows a write cycle followed by a read cycle in continuous page mode. The
read hits in the same page as the write so RAS
is not negated before the second cycle. Note
that the row address does not appear on the pins for a bus cycle that hits in the page. Column
addresses are immediately multiplexed onto the pins. The third bus cycle is a page miss, so
RAS
is precharged before the end of the bus cycle and no extra precharge delay is incurred.
Figure 11-9. Continuous Page-Mode Operation
If a write cycle hits in the page, CAS must be delayed by one clock to allow data to become
valid, as shown in Figure 11-10.
A[31:0]
RAS
[1] or [0]
CAS
[3:0]
DRAMW
D[31:0]
RCD=0
RNCN=1
CAS=01
Bus Cycle 1 Bus Cycle 2 Bus Cycle 3
Page Hit
Page Miss
Row Column Column Row Column
CLKIN