Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-17
Synchronous Operation
SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data
pipelines and commands to initiate special actions. Commands are issued to memory using
specific encodings on address and control pins. Soon after system reset, a command must
be sent to the SDRAM mode register to configure SDRAM operating parameters. Note that,
after synchronous operation is selected by setting DCR[SO], DRAM controller registers
reflect the synchronous operation and there is no way to return to asynchronous operation
without resetting the processor.
11.4.1 DRAM Controller Signals in Synchronous Mode
Table 11-11 shows the behavior of DRAM signals in synchronous mode.
Table 11-10. SDRAM Commands
Command Definition
ACTV Activate. Executed before READ or WRITE executes; SDRAM registers and decodes row address.
MRS Mode register set.
NOP No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; RAS asserted.
PALL Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is
opened.
READ Read access. SDRAM registers column address and decodes that a read access is occurring.
REF Refresh. Refreshes internal bank rows of an SDRAM component.
SELF Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode.
SELFX Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared.
WRITE Write access. SDRAM registers column address and decodes that a write access is occurring.
Table 11-11. Synchronous DRAM Signal Connections
Signal Description
SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched
by the SDRAM. SRAS
should be connected to the corresponding SDRAM SRAS. Do not confuse SRAS
with the DRAM controller’s RAS
[1:0], which should not be interfaced to the SDRAM SRAS signals.
SCAS
Synchronous column address strobe. Indicates a valid column address is present and can be latched by
the SDRAM. SCAS
should be connected to the corresponding signal labeled SCAS on the SDRAM. Do
not confuse SCAS
with the DRAM controller’s CAS[3:0] signals.
DRAMW
DRAM read/write. Asserted for write operations and negated for read operations.
RAS
[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5407. One RAS
signal selects one SDRAM block and connects to the corresponding CS
signals.
SCKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs.
Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down
mode where operations are suspended or they can enter self-refresh mode. SCKE functionality is
controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SCKE to provide
command-bit functionality.
CAS
[3:0] Column address strobe. For synchronous operation, CAS[3:0] function as byte enables to the SDRAMs.
They connect to the DQM signals (or mask qualifiers) of the SDRAMs.