Datasheet

11-18 MCF5407 User’s Manual
Synchronous Operation
Figure 11-13 shows a typical signal configuration for synchronous mode.
Figure 11-13. MCF5407 SDRAM Interface
11.4.2 Using Edge Select (EDGESEL)
EDGESEL can ease system-level timings (note that the optional buffer in Figure 11-13 is
for memories that need extra delay). The clock at the input to the SDRAM is monitored and
data is held until the next edge of the bus clock, adding required output hold time to the
address, data, and control signals.
To generate SDRAM interface timing, address, data, and control signals are clocked
through a two-stage shift register. The first stage is clocked on the rising edge of CLKIN;
the second is clocked on the falling edge. This makes the signal available for up to an
additional half bus clock cycle, of which only a small amount is needed for proper timing.
Using the connection shown in Figure 11-13 ensures that data remains held for a longer
time after the rising edge of the SDRAM clock input. This helps to match the MCF5407
output timing with the SDRAM clock.
Figure 11-14 shows the output wave forms for the interface signals changing on the rising
edge (A) and falling edge (B) of CLKIN as determined by whether EDGESEL is tied high
or low. It also shows timing (C) with EDGESEL tied to buffered CLKIN.
CLKIN Bus clock output. Connects to the CLK input of SDRAMs.
EDGESEL Synchronous edge select. Provides additional output hold time for signals that interface to external
SDRAMs. EDGESEL supports the three following modes for SDRAM interface signals:
• Tied high. Signals change on the rising edge of CLKIN.
• Tied low. Signals change on the falling edge of CLKIN.
• Tied to buffered CLKIN. Signals change on the rising edge of the buffered clock.
EDGESEL can provide additional output hold time for SDRAM interface signals, however the SDRAM
clock and CLKIN frequencies must be the same. See Section 11.4.2, “Using Edge Select (EDGESEL).”
Table 11-11. Synchronous DRAM Signal Connections (Continued)
Signal Description
EDGESEL
A[31:0]
CAS
DRAMW
SCAS
SRAS
SCKE
CKE
CAS
RAS
DQM
WE
ADDRESS
DATA
CLK
MCF5407
CLKIN
D[31:0]
SDRAM
1
Trace length from buffer to CLK must equal length from buffer to EDGESEL.
CLKIN
1