Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-19
Synchronous Operation
Figure 11-14. Using EDGESEL to Change Signal Timing
11.4.3 Synchronous Register Set
The memory map in Table 11-1 is the same for both synchronous and asynchronous
operation. However, some bits are different, as noted in the following sections.
11.4.3.1 DRAM Control Register (DCR) in Synchronous Mode
The DRAM control register (DCR), Figure 11-15, controls refresh logic.
Table 11-12 describes DCR fields.
1514131211109876543210
Field SO — NAM COC IS RTIM RC
Reset 0 Uninitialized
R/W R/W
Addr MBAR + 0x100
Figure 11-15. DRAM Control Register (DCR) (Synchronous Mode)
Table 11-12. DCR Field Descriptions (Synchronous Mode)
Bits Name Description
15 SO Synchronous operation. Selects synchronous or asynchronous mode. When in synchronous mode,
the DRAM controller can be switched to ADRAM mode only by resetting the MCF5407.
0 Asynchronous DRAMs. Default at reset.
1 Synchronous DRAMs
14 — Reserved, should be cleared.
13 NAM No address multiplexing. Some implementations require external multiplexing. For example, when
linear addressing is required, the DRAM should not multiplex addresses on DRAM accesses.
0 The DRAM controller multiplexes the external address bus to provide column addresses.
1 The DRAM controller does not multiplex the external address bus to provide column addresses.
VALID VALID VALID VALID
CLKIN
Address/
VALID VALID VALID
Buffered
VALID VALID VALIDVALID
A: Address and Data Timing with EDGESEL Tied High
B: Address and Data Timing with EDGESEL Tied Low
Data
Address/
Data
C: Address and Data Timing with EDGESEL Tied to Buffered Clock
Address/
Data
CLKIN
Buffer Delay
CLKIN
CLKIN