Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-27
Synchronous Operation
11.4.4.2 Interfacing Example
The tables in the previous section can be used to configure the interface in the following
example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the
MCF5407, the connections would be as shown in Table 11-31.
11.4.4.3 Burst Page Mode
SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS
is issued, the SDRAM accepts a new address and asserts SCAS every clock for as long as
accesses are in that page. In burst page mode, there are multiple read or write operations for
every
ACTV command in the SDRAM if the requested transfer size exceeds the port size of
the associated SDRAM. The primary cycle of the transfer generates the
ACTV and READ or
WRITE commands; secondary cycles generate only READ or WRITE commands. As soon as
the transfer completes, the
PALL command is generated to prepare for the next access.
Note that in synchronous operation, burst mode and address incrementing during burst
cycles are controlled by the MCF5407 DRAM controller. Thus, instead of the SDRAM
enabling its internal burst incrementing capability, the MCF5407 controls this function.
This means that the burst function that is enabled in the mode register of SDRAMs must be
disabled when interfacing to the MCF5407.
Figure 11-18 shows a burst read operation. In this example, DACR[CASL] = 01, for an
SRAS
-to-SCAS delay (t
RCD
) of 2 CLKIN cycles. Because t
RCD
is equal to the read CAS
Table 11-29. MCF5407 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF5407
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31
Row 151413121110 9 171921232425262728293031
Column 234567816182022
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 11-30. MCF5407 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5407
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31
Row 151413121110 9 1719212325262728293031
Column 23456781618202224
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
Table 11-31. SDRAM Hardware Connections
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1
MCF5407
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22