Datasheet
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A
Part II
Part IV
Part III
6
GLO
IND
Part I
Overview
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
SIM Overview
Phase-Locked Loop (PLL)
I
2
C Module
Interrupt Controller
Chip-Select Module
Synchronous/Asynchronous DRAM Controller Module
DMA Controller Module
Timer Module
UART Modules
Parallel Port (General-Purpose I/O)
Appendix A: Migration
Mechanical Data
Signal Descriptions
Bus Operation
IEEE 1149.1 Test Access Port (JTAG)
Electrical Specifications
Part I: MCF5407
Processor
Core
Part II: System Integration Module (
SIM)
Part IV: Hardware Interface
Part III: Peripheral Module
Glossary of Terms and Abbreviations
Index
Appendix B: Memory Map
B
20
B
GLO
IND
IND
