Datasheet

xxx MCF5407 User’s Manual
TABLES
Table
Number
Title
Page
Number
4-10 Data Cache Line State Transitions (Current State Modified)..................................... 4-31
5-1 Debug Module Signals.................................................................................................. 5-2
5-2 PSTDDATA: Sequential Execution of Single-Cycle Instructions .............................. 5-3
5-3 PSTDDATA: Data Operand Captured.......................................................................... 5-4
5-4 Processor Status Encoding............................................................................................ 5-5
5-5 0xE Status Posting ........................................................................................................ 5-7
5-6 BDM/Breakpoint Registers........................................................................................... 5-9
5-7 AATR and AATR1 Field Descriptions....................................................................... 5-11
5-8 ABLR and ABLR1 Field Description......................................................................... 5-12
5-9 ABHR and ABHR1 Field Description........................................................................ 5-12
5-10 BAAR Field Descriptions........................................................................................... 5-13
5-11 CSR Field Descriptions............................................................................................... 5-14
5-12 DBRn Field Descriptions............................................................................................ 5-16
5-13 DBMRn Field Descriptions ........................................................................................ 5-16
5-14 Access Size and Operand Data Location .................................................................... 5-16
5-15 PBR, PBR1, PBR2, PBR3 Field Descriptions............................................................ 5-17
5-16 PBMR Field Descriptions........................................................................................... 5-17
5-17 TDR Field Descriptions .............................................................................................. 5-19
5-18 XTDR Field Descriptions ........................................................................................... 5-20
5-19 Receive BDM Packet Field Description ..................................................................... 5-25
5-20 Transmit BDM Packet Field Description ................................................................... 5-26
5-21 BDM Command Summary ......................................................................................... 5-26
5-22 BDM Field Descriptions............................................................................................. 5-27
5-23 Control Register Map.................................................................................................. 5-42
5-24 Definition of DRc Encoding—Read........................................................................... 5-44
5-25 PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response......................................... 5-46
5-26 Exception Vector Assignments................................................................................... 5-47
5-27 PSTDDATA Specification for User-Mode Instructions............................................. 5-50
5-28 PSTDDATA Specification for Supervisor-Mode Instructions ................................... 5-54
6-1 SIM Registers .............................................................................................................. 6-3
6-2 MBAR Field Descriptions ............................................................................................ 6-5
6-3 RSR Field Descriptions................................................................................................. 6-6
6-4 SYPCR Field Descriptions ........................................................................................... 6-8
6-5 PLLIPL Settings.......................................................................................................... 6-10
6-6 MPARK Field Descriptions........................................................................................ 6-11
7-1 Divide Ratio Encodings ............................................................................................... 7-2
7-2 PLLCR Field Descriptions............................................................................................ 7-3
7-3 PLL Module Input SIgnals............................................................................................ 7-4
7-4 PLL Module Output Signals ......................................................................................... 7-4
8-1 I
2
C Interface Memory Map........................................................................................... 8-6
8-2 I
2
C Address Register Field Descriptions ...................................................................... 8-6
8-3 IFDR Field Descriptions ............................................................................................... 8-7
8-4 I
2
CR Field Descriptions................................................................................................ 8-8