Datasheet

11-32 MCF5407 User’s Manual
Synchronous Operation
Figure 11-22. Auto-Refresh Operation
11.4.4.6 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at
the same time to perform an internal refresh operation and to maintain the integrity of the
data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS].
When IS is set, the
SELF command is sent to the SDRAM. When IS is cleared, the SELFX
command is sent to the DRAM controller. Figure 11-23 shows the self-refresh operation.
Figure 11-23. Self-Refresh Operation
11.4.5 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller
A[31:0]
SRAS
SCAS
DRAMW
PALL NOPNOP
RAS[0] or [1]
REF ACTV
t
RCD
= 2
t
RC
= 6
CLKIN
SRAS
SCAS
DRAMW
PALL NOPNOP
RAS[0] or [1]
SELF
First
SCKE
Possible
ACTV
SELFX
Self-
Refresh
Active
t
RCD
= 2
t
RC
= 6
CLKIN
(DCR[COC] = 0)