Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-35
SDRAM Example
11.5.2 DCR Initialization
At power-up, the DCR has the following configuration if synchronous operation and
SDRAM address multiplexing is desired.
This configuration results in a value of 0x8026 for DCR, as shown in Table 11-34.
11.5.3 DACR Initialization
As shown in Figure 11-26, in this example the SDRAM is programmed to access only the
second 512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The
starting address of the SDRAM is 0xFF80_0000. Continuous page mode feature is used.
Table 11-33. SDRAM Hardware Connections
MCF5407
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1
15 14 13 12 11 10 9 8 0
Field SO res NAM COC IS RTIM RC
Setting 1 X 00000000100110
(hex)8026
Figure 11-25. Initialization Values for DCR
Table 11-34. DCR Initialization Values
Bits Name Setting Description
15 SO 1 Indicating synchronous operation
14 — x Don’t care (reserved)
13 NAM 0 Indicating SDRAM controller multiplexes address lines internally
12 COC 0 SCKE is used as clock enable instead of command bit because user is not multiplexing
address lines externally and requires external command feed.
11 IS 0 At power-up, allowing power self-refresh state is not appropriate because registers are
being set up.
10–9 RTIM 00 Because t
RC
value is 70 nS, indicating a 3-clock refresh-to-ACTV timing.
8–0 RC 0x26 Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every
15.625 µs for each row, or 625 bus clocks at 40 MHz. Because DCR[RC] is incremented by
1 and multiplied by 16, RC = (625 bus clocks/16) -1 = 38.06 = 0x38