Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-37
SDRAM Example
11.5.4 DMR Initialization
In this example, again, only the second 512-Kbyte block of each 1-Mbyte space is accessed
in each bank. In addition the SDRAM component is mapped only to readable and writable
supervisor and user data. The DMRs have the following configuration.
With this configuration, the DMR0 = 0x0074_0075, as described in Table 11-36.
2 PM 1 Indicates continuous page mode
1–0 — Reserved. Don’t care.
31 18 17 16
Field BAM —
Setting 00000000011101XX
(hex) 0 0 7 4
15 9876543210
Field — WP — C/I AM SC SD UC UD V
Setting XXXXXXX0X1110101
(hex)0075
Figure 11-28. DMR0 Register
Table 11-36. DMR0 Initialization Values
Bits Name Setting Description
31–16 BAM With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits and
upper 512K select bits unmasked. Note that bits 22 and 21 are set because they are used
as bank selects; bit 20 is set because it controls the 1-Mbyte boundary address.
15–9 — Reserved. Don’t care.
8 WP 0 Allow reads and writes
7 — Reserved
6 C/I 1 Disable CPU space access
5 AM 1 Disable alternate master access
4 SC 1 Disable supervisor code accesses
3 SD 0 Enable supervisor data accesses
2 UC 1 Disable user code accesses
1 UD 0 Enable user data accesses
0 V 1 Enable accesses.
Table 11-35. DACR Initialization Values
Bits Name Setting Description