Datasheet

Tables xxxi
TABLES
Table
Number
Title
Page
Number
8-5 I2SR Field Descriptions................................................................................................ 8-9
9-1 Interrupt Controller Registers ....................................................................................... 9-2
9-2 Interrupt Control Registers ........................................................................................... 9-2
9-3 ICRn Field Descriptions ............................................................................................... 9-3
9-4 Interrupt Priority Scheme.............................................................................................. 9-4
9-5 AVR Field Descriptions................................................................................................ 9-6
9-6 Autovector Register Bit Assignments........................................................................... 9-6
9-7 IPR and IMR Field Descriptions................................................................................... 9-7
9-8 IRQPAR Field Descriptions ......................................................................................... 9-8
10-1 Chip-Select Module Signals ....................................................................................... 10-1
10-2 Byte Enables/Byte Write Enable Signal Settings ....................................................... 10-2
10-3 Accesses by Matches in CSCRs and DACRs ............................................................. 10-3
10-4 D7/AA, Automatic Acknowledge of Boot CS0.......................................................... 10-4
10-5 D[6:5]/PS[1:0], Port Size of Boot CS0....................................................................... 10-5
10-6 D3/BE_CONFIG0, BE
[3:0] Boot Configuration ....................................................... 10-5
10-7 Chip-Select Registers.................................................................................................. 10-5
10-8 CSARn Field Description ........................................................................................... 10-7
10-9 CSMRn Field Descriptions......................................................................................... 10-7
10-10 CSCRn Field Descriptions.......................................................................................... 10-8
11-1 DRAM Controller Registers ....................................................................................... 11-3
11-2 SDRAM Signal Summary .......................................................................................... 11-4
11-3 DCR Field Descriptions (Asynchronous Mode)......................................................... 11-5
11-4 DACR0/DACR1 Field Description ............................................................................ 11-6
11-5 DMR0/DMR1 Field Descriptions............................................................................... 11-7
11-6 Generic Address Multiplexing Scheme ...................................................................... 11-8
11-7 DRAM Addressing for Byte-Wide Memories.......................................................... 11-10
11-8 DRAM Addressing for 16-Bit Wide Memories........................................................ 11-10
11-9 DRAM Addressing for 32-Bit Wide Memories........................................................ 11-11
11-10 SDRAM Commands ................................................................................................. 11-17
11-11 Synchronous DRAM Signal Connections ................................................................ 11-17
11-12 DCR Field Descriptions (Synchronous Mode) ......................................................... 11-19
11-13 DACR0/DACR1 Field Descriptions (Synchronous Mode)...................................... 11-21
11-14 DMR0/DMR1 Field Descriptions............................................................................. 11-23
11-15 MCF5407 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 11-24
11-16 MCF5407 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 11-24
11-17 MCF5407 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................. 11-24
11-18 MCF5407 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................. 11-24
11-19 MCF5407 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 11-25
11-20 MCF5407 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 11-25
11-21 MCF5407 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)................ 11-25
11-22 MCF5407 to SDRAM Interface (16-Bit Port, 10-Column Address Lines).............. 11-25
11-23 MCF5407 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 11-25
11-24 MCF5407 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 11-26