Datasheet

Chapter 12. DMA Controller Module 12-7
DMA Controller Module Programming Model
12.4.1 Source Address Registers (SAR0–SAR3)
SARn, Figure 12-5, contains the address from which the DMA controller requests data. In
single-address mode, SARn provides the address regardless of the direction.
NOTE:
SAR/DAR address ranges cannot be programmed to on-chip
SRAM because it cannot be accessed by on-chip DMA.
12.4.2 Destination Address Registers (DAR0–DAR3)
For dual-address transfers only, DARn, Figure 12-6, holds the address to which the DMA
controller sends data.
Figure 12-6. Destination Address Registers (DARn)
NOTE:
On-chip DMAs do not maintain coherency with MCF5407
caches and so must not transfer data to cacheable memory.
12.4.3 Byte Count Registers (BCR0–BCR3)
BCRn, Figure 12-7, holds the number of bytes yet to be transferred for a given block. BCRn
decrements on the successful completion of the address transfer of either a write transfer in
dual-address mode or any transfer in single-address mode. BCRn decrements by 1, 2, 4, or
16 for byte, word, longword, or line accesses, respectively.
31 0
Field SAR
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W R/W
Address MBAR + 0x300, 0x340, 0x380, 0x3C0
Figure 12-5. Source Address Registers (SARn)
31 0
Field DAR
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W R/W
Address MBAR + 304, 0x344, 0x384, 0x3C4