Datasheet

xxxii MCF5407 User’s Manual
TABLES
Table
Number
Title
Page
Number
11-25 MCF5407 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ............. 11-26
11-26 MCF5407 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26
11-27 MCF5407 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26
11-28 MCF5407 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 11-26
11-29 MCF5407 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 11-27
11-30 MCF5407 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 11-27
11-31 SDRAM Hardware Connections............................................................................... 11-27
11-32 SDRAM Example Specifications ............................................................................. 11-34
11-33 SDRAM Hardware Connections............................................................................... 11-35
11-34 DCR Initialization Values......................................................................................... 11-35
11-35 DACR Initialization Values...................................................................................... 11-36
11-36 DMR0 Initialization Values...................................................................................... 11-37
11-37 Mode Register Initialization ..................................................................................... 11-38
12-1 DMA Signals .............................................................................................................. 12-2
12-2 MCF5407 Signal Configurations for PP[4:2]/TM[2:0]/D
ACK[1:0] .......................... 12-3
12-3 Memory Map for DMA Controller Module Registers................................................ 12-6
12-4 DCRn Field Descriptions............................................................................................ 12-8
12-5 DSRn Field Descriptions .......................................................................................... 12-10
13-1 General-Purpose Timer Module Memory Map .......................................................... 13-3
13-2 TMRn Field Descriptions ........................................................................................... 13-4
13-3 TERn Field Descriptions............................................................................................. 13-6
13-4 Time-Out Values (in Seconds)—TRR[REF] = 0xFFFF(162-MHz Processor Clock)13-7
14-1 UART Module Programming Model.......................................................................... 14-4
14-2 UMR1n Field Descriptions......................................................................................... 14-6
14-3 UMR2n Field Descriptions......................................................................................... 14-7
14-4 RXLVL Field Descriptions......................................................................................... 14-8
14-5 Modem Control Register (MODCTL) Field Descriptions.......................................... 14-9
14-6 TXLVL Field Descriptions ....................................................................................... 14-10
14-7 USRn Field Descriptions .......................................................................................... 14-11
14-8 UCSRn Field Descriptions........................................................................................ 14-12
14-9 RSMP Field Descriptions ......................................................................................... 14-13
14-10 TSPC Field Descriptions........................................................................................... 14-13
14-11 UCRn Field Descriptions.......................................................................................... 14-14
14-12 UIPCRn Field Descriptions ...................................................................................... 14-17
14-13 UACRn Field Descriptions....................................................................................... 14-18
14-14 UISRn/UIMRn Field Descriptions ........................................................................... 14-19
14-15 UIVRn Field Descriptions ........................................................................................ 14-20
14-16 UIPn Field Descriptions............................................................................................ 14-20
14-17 UOP1/UOP0 Field Descriptions ............................................................................... 14-21
14-18 UART Module Signals ............................................................................................. 14-22
14-19 UART Module Initialization Sequence .................................................................... 14-38
15-1 Parallel Port Pin Descriptions ..................................................................................... 15-2
15-2 PADDR Field Description .......................................................................................... 15-2