Datasheet

12-10 MCF5407 User’s Manual
DMA Controller Module Programming Model
12.4.5 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
Figure 12-9. Only a write to DSRn[DONE] results in action.
Table 12-5 describes DSRn fields.
15 AT DMA acknowledge type. Controls whether acknowledge information is provided for the entire
transfer or only the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the
result of an external request.
1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information
is displayed for both the read and write cycles.
14–0 — Reserved, should be cleared.
76543210
Field — CE BES BED — REQ BSY DONE
Reset — 000— 000
R/W R/W
Address MBAR + 0x310, 0x350, 0x390, 0x3D0
Figure 12-9. DMA Status Registers (DSRn)
Table 12-5. DSRn Field Descriptions
Bits Name Description
7 — Reserved, should be cleared.
6 CE Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size,
or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by
writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
5 BES Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error either during the read portion of a transfer or
during an access in single-address mode (SAA = 1).
4 BED Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
3 — Reserved, should be cleared.
2 REQ Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
Table 12-4. DCRn Field Descriptions (Continued)
Bits Name Description