Datasheet

13-2 MCF5407 User’s Manual
General-Purpose Timer Units
13.1.1 Key Features
Each general-purpose 16-bit timer unit has the following features:
• Maximum period of 4.97 seconds at 54 MHz
• 18.5-nS resolution at 54 MHz
• Programmable sources for the clock input, including external clock
• Input-capture capability with programmable trigger edge on input pin
• Output-compare with programmable mode for the output pin
• Free run and restart modes
• Maskable interrupts on input capture or reference-compare
13.2 General-Purpose Timer Units
The general-purpose timer units provide the following features:
• Each timer can be programmed to count and compare to a reference value stored in
a register or capture the timer value at an edge detected on TIN.
• System bus clock can be divided by 16 or 1. This clock is input to the prescaler.
• TIN is fed directly into the 8-bit prescaler. The maximum value of TIN is 1/5 of
CLKIN, as described in Chapter 20, “Electrical Specifications.”
• The 8-bit prescaler clock divides the clocking source and is user-programmable
from 1 to 256.
• Programmed events generate interrupts.
• The timer output signal (TOUT) can be configured to toggle or pulse on an event.
13.3 General-Purpose Timer Programming Model
The following features are programmable through the timer registers, shown in Table 13-1:
• Prescaler—The prescaler clock input is selected from CLKIN (divided by 1 or 16)
or from the corresponding timer input, TIN. TIN is synchronized to CLKIN. The
synchronization delay is between two and three CLKIN clocks. The corresponding
TMRn[ICLK] selects the clock input source. A programmable prescaler divides the
clock input by values from 1 to 256. The prescaler is an input to the 16-bit counter.
• Capture mode—Each timer has a 16-bit timer capture register (TCR0 and TCR1)
that latches the counter value when the corresponding input capture edge detector
senses a defined TIN transition. The capture edge bits (TMRn[CE]) select the type
of transition that triggers the capture, sets the timer event register capture event bit,
TERn[CAP], and issues a maskable interrupt.