Datasheet

13-4 MCF5407 User’s Manual
General-Purpose Timer Programming Model
13.3.2 Timer Reference Registers (TRR0/TRR1)
Each timer reference register (TRR0/TRR1), Figure 13-3, contains the reference value
compared with the respective free-running timer counter (TCN0/TCN1) as part of the
output-compare function. The reference value is not matched until TCNn equals TRRn.
=
13.3.3 Timer Capture Registers (TCR0/TCR1)
Each timer capture register (TCR0/TCR1), Figure 13-4, latches the corresponding TCNn
value during a capture operation when an edge occurs on TIN, as programmed in TMRn.
CLKIN is assumed to be the clock source. TIN cannot simultaneously function as a
Table 13-2. TMRn Field Descriptions
Bits Name Description
15–8 PS Prescaler value. The prescaler is programmed to divide the clock input (CLKIN/(16 or 1) or clock on
TIN) by values from 1 (PS = 0000_0000) to 256 (PS = 1111_1111).
7–6 CE Capture edge and enable interrupt
00 Disable interrupt on capture event
01 Capture on rising edge only and enable interrupt on capture event
10 Capture on falling edge only and enable interrupt on capture event
11 Capture on any edge and enable interrupt on capture event
5 OM Output mode
0 Active-low pulse for one CLKIN cycle (18.5 ns at 54 MHz).
1 Toggle output.
4 ORI Output reference interrupt enable. If ORI is set when TERn[REF] = 1, an interrupt occurs.
0 Disable interrupt for reference reached (does not affect interrupt on capture function).
1 Enable interrupt upon reaching the reference value.
3 FRR Free run/restart
0 Free run. Timer count continues to increment after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
2–1 CLK Input clock source for the timer
00 Stop count
01 System bus clock divided by 1
10 System bus clock divided by 16. Note that this clock source is not synchronized to the timer; thus
successive time-outs may vary slightly.
11 TIN pin (falling edge)
0 RST Reset timer. Performs a software timer reset similar to an external reset, although other register
values can still be written while RST = 0. A transition of RST from 1 to 0 resets register values. The
timer counter is not clocked unless the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
15 0
Field REF
Reset 1111_1111_1111_1111
R/W R/W
Address MBAR + 0x144 (TRR0),+ 0x184 (TRR1)
Figure 13-3. Timer Reference Registers (TRR0/TRR1)