Datasheet

xxxiv MCF5407 User’s Manual
TABLES
Table
Number
Title
Page
Number
20-7 Output AC Timing Specification ................................................................................ 20-6
20-8 Reset Timing Specification....................................................................................... 20-15
20-9 Debug AC Timing Specification .............................................................................. 20-16
20-10 Timer Module AC Timing Specification.................................................................. 20-17
20-11 I
2
C Input Timing Specifications between SCL and SDA......................................... 20-18
20-12 I
2
C Output Timing Specifications between SCL and SDA...................................... 20-18
20-13 UART Module AC Timing Specifications ............................................................... 20-19
20-14 General-Purpose I/O Port AC Timing Specifications............................................... 20-22
20-15 DMA AC Timing Specifications .............................................................................. 20-23
20-16 IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................... 20-24
A-1 Differences between MCF5307 and MCF5407........................................................... A-1
A-2 MOVEC CPU Space Register Map ............................................................................. A-4
A-3 TM[2:1] Encoding for MCF5307 Internal DMA as Master (TT = 01) ....................... A-4
A-4 TM0 Encoding for MCF5307 Internal DMA as Master (TT = 01) ............................. A-5
A-5 Divide Ratio Encodings ............................................................................................... A-7
A-6 D[7:0] Multiplexing..................................................................................................... A-8
A-7 D7/AA, Automatic Acknowledge of Boot CS0........................................................... A-9
A-8 D[6:5]/PS[1:0], Port Size of Boot CS0 ........................................................................ A-9
A-9 D4/ADDR_CONFIG, Address Pin Assignment.......................................................... A-9
A-10 D3/BE_CONFIG, BE[3:0] Boot Configuration .......................................................... A-9
A-11 Definition of DRc Encoding—Write ......................................................................... A-13
A-12 Debug C Exception Vector Assignments .................................................................. A-16
A-13 Version 4 Debug C Processor Status Encodings ....................................................... A-17
B-1 SIM Registers................................................................................................................B-1
B-2 Interrupt Controller Registers .......................................................................................B-1
B-3 Chip-Select Registers....................................................................................................B-2
B-4 DRAM Controller Registers .........................................................................................B-3
B-5 General-Purpose Timer Registers .................................................................................B-4
B-6 UART0 Control Registers.............................................................................................B-4
B-7 UART1 Control Registers.............................................................................................B-6
B-8 Parallel Port Memory Map............................................................................................B-7
B-9 I
2
C Interface Memory Map...........................................................................................B-8
B-10 DMA Controller Registers............................................................................................B-8