Datasheet
14-2 MCF5407 User’s Manual
Serial Module Overview
the channel transmitter serial data output (TxD). See Section 14.5.2.1, “Transmitting in
UART Mode.”
The receiver converts serial data from the channel receiver serial data input (RxD) to
parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers
the assembled character onto the bus during read operations. The receiver may be polled-
or interrupt-driven. See Section 14.5.2.3, “Receiver.”
UART1 can be programmed to function like original UART (identical to UART0) or in one
of the following three modem modes:
• An 8-bit CODEC interface
• A 16-bit CODEC interface
• An audio CODEC ‘97 (AC ’97) digital interface controller
A CODEC (code/decode) chip provides a data conversion interface for high-speed modem
designs meeting a high range of standards, such as ITU-T V.34 and PCM. UART1
interfaces to the CODEC through a serial port consisting of Tx and Rx serial data and serial
bit clock and frame inputs from the CODEC. UART1 transfers digital sample data to and
from the CODEC through the serial port.
AC ’97 defines an architecture for audio-intensive personal computer applications such as
gaming, authoring, and high-resolution music and video playback. An external AC ’97
analog device performs mixing, analog processing, and sample-rate DAC and ADC.
UART1 interfaces to the AC ’97 device through a serial port consisting of Tx and Rx serial
data, a serial bit clock, and a frame sync output generated by UART1 from the serial bit
clock. An MCF5407 general-purpose I/O (GPIO) is used as a reset to the AC ‘97 device.
UART1 transfers digital sample data as well as control/status information to and from the
AC ‘97 device through the serial port.
Unless otherwise specified, descriptions in this chapter refer to UART mode.
14.2 Serial Module Overview
The MCF5407 contains two independent UART modules, whose features are as follows:
• Each can be clocked by CLKIN, eliminating a need for an external crystal
• Full-duplex asynchronous/synchronous receiver/transmitter channel
• Quadruple-buffered receiver
• Double-buffered transmitter
• Independently programmable receiver and transmitter clock sources
• Programmable data format:
— 5–8 data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two stop bits
