Datasheet

14-4 MCF5407 User’s Manual
Register Descriptions
Table 14-1. UART Module Programming Model
MBAR Offset
[31:24] [23:16] [15:8] [7:0]
UART0 UART1
0x1C0 0x200 UART mode
registers
1
—(UMR1n)
[p. 14-5], (UMR2n) [p.
14-7]
Rx FIFO threshold
register—(RXLVL) [p.
14-8] (UART1 only)
Modem control
register—(MODCTL)
[p. 14-9] (UART1 only)
Tx FIFO threshold
register—(TXLVL) [p.
14-10] (UART1 only)
0x1C4 0x204 (Read) UART status
registers—(USRn) [p.
14-10]
— (Read) Rx samples
available
register—(RSMP) [p.
14-12] (UART1 only)
(Read) Tx space
available
register—(TSPC) [p.
14-12] (UART1 only)
(Write) UART
clock-select
register
1
—(UCSRn)
[p. 14-12]
0x1C8 0x208 (Read) Do not access
2
—
(Write) UART
command
registers—(UCRn) [p.
14-13]
—
0x1CC 0x20C (UART0/Read) UART
receiver
buffers—(URBn) [p.
14-15]
—
(UART1/Read) UART receiver buffers—(URBn) [p. 14-15]
(UART0/Write) UART
transmitter
buffers—(UTBn) [p.
14-16]
—
(UART1/Write) UART transmitter buffers—(UTBn) [p. 14-16]
0x1D0 0x210 (Read) UART input
port change
registers—(UIPCRn)
[p. 14-17]
—
(Write) UART auxiliary
control
registers
1
—(UACRn)
[p. 14-17]
—
0x1D4 0x214 (Read) UART interrupt
status
registers—(UISRn) [p.
14-18]
—
(Write) UART interrupt
mask
registers—(UIMRn) [p.
14-18]
—
0x1D8 0x218 UART divider upper
registers—(UDUn) [p.
14-19]
—