Datasheet

14-10 MCF5407 User’s Manual
Register Descriptions
14.3.5 Tx FIFO Threshold Register (TXLVL)
Tx FIFO threshold register (TXLVL) supports only UART1 in both UART and modem
modes. TXLVL holds the Tx FIFO threshold, the value at which the Tx FIFO is considered
to be empty for purposes of alerting the CPU that the Tx FIFO needs more data/samples.
Table 14-6 describes TXLVL fields.
14.3.6 UART Status Registers (USRn)
The USRn, Figure 14-7, shows status of the transmitter, the receiver, and the FIFO.
Table 14-7 describes USRn fields.
754 0
Field — TXLVL
Reset — 0_0000
R/W R/W
Address MBAR + 0x203
Figure 14-6. Tx FIFO Threshold Register (TXLVL)
Table 14-6. TXLVL Field Descriptions
Bits Name Description
7–5 — Reserved, should be cleared.
4–0 TXLVL Tx FIFO empty threshold level. 0000–1111 selects values of 0–31 bytes, respectively. The Tx FIFO
is empty when the number of bytes in the FIFO is less than or equal to the Tx threshold value.
Although the FIFO thresholds are in numbers of bytes, data is written into and read out of the
FIFOs in numbers of samples, as follows:
1 sample = 1 byte for 8-bit CODEC and UART modes
1 sample = 2 bytes for 16-bit CODEC and AC ‘97 modes
For choosing threshold values, AC ‘97 samples should be thought of as 2-byte entities.
Choose the Tx threshold register value using the following formula:
TXLVL = (# samples) * (# bytes per sample)
For example, to indicate empty when three or fewer samples remain, calculate TXLVL as follows:
For 8-bit CODEC or UART mode, TXLVL = (3 samples) * (1 byte per sample) = 3 bytes
For 16-bit CODEC or AC ‘97 modes, TXLVL = (3 samples) * (2 bytes per sample) = 6 bytes
76543210
Field RB FE PE OE TxEMP TxRDY FFULL RxRDY
Reset 0000_0000
R/W Read only
Address MBAR + 0x1C4 (USR0), 0x204 (USR1)
Figure 14-7. UART Status Register (USRn)