Datasheet

14-20 MCF5407 User’s Manual

14.3.17 UART Interrupt Vector Register (UIVRn)

The UIVRn, Figure 14-21, contain the 8-bit internal interrupt vector number (IVR).

Table 14-15 describes UIVRn ﬁelds.

14.3.18 UART Input Port Register (UIPn)

The UART input port registers (UIPn), Figure 14-22, show the current state of the CTS

input when the processor is in UART mode.

Table 14-16 describes UIPn ﬁelds.

7 0

Field IVR

Reset 0000_1111

R/W R/W

Address MBAR + 0x1F0 (UIVR0), 0x230 (UIVR1)

Figure 14-21. UART Interrupt Vector Register (UIVRn)

Table 14-15. UIVRn Field Descriptions

Bits Name Description

7–0 IVR Interrupt vector. Indicates the vector number where the address of the exception handler for the

speciﬁed interrupt is located. UIVRn is reset to 0x0F, indicating an uninitialized interrupt condition.

7 10

Field — CTS

Reset 1111_1111

R/W Read only

Address MBAR + 0x1F4 (UIP0), 0x234 (UIP1)

Figure 14-22. UART Input Port Register (UIPn)

Table 14-16. UIPn Field Descriptions

Bits Name Description

7–1 — Reserved, should be cleared.

0 CTS Current state. The CTS value is latched and reﬂects the state of the input pin when UIPn is read.

Note: This bit has the same function and value as UIPCRn[RTS].

0 The current state of the CTS

input is logic 0.

1 The current state of the CTS

input is logic 1.

When UART1 is in modem mode, CTS

toggles when a frame sync occurs. It is used during testing to

synchronize test code running on the CPU with frames transferred on the serial interface.