Datasheet

Chapter 14. UART Modules 14-21
UART Module Signal Definitions
14.3.19 UART Output Port Data Registers (UOP1n/UOP0n)
In UART mode, the RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated
by writing a 1 to UOP0n[RTS]. UOP registers have no effect in modem mode. See
Figure 14-23.
Table 14-17 describes UOP1 fields.
14.4 UART Module Signal Definitions
Figure 14-24 shows both the external and internal signal groups.
Figure 14-24. UART Block Diagram Showing External and Internal Interface Signals
7 10
Field — RTS
Reset 0000_0000
R/W Write only
Addr UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0)
Figure 14-23. UART Output Port Data 1 Register (UOP1/UOP0)
Table 14-17. UOP1/UOP0 Field Descriptions
Bits Name Description
7–1 — Reserved, should be cleared.
0 RTS Output port parallel output. Controls assertion (UOP1)/negation (UOP0) of RTS output.
0 Not affected.
1 Asserts R
TS (UOP1). Negates RTS (UOP0).
Internal
Four-Character
Receive Buffer
Two-Character
Transmit Buffer
Input Port
Output Port
Interface
UART Module
Address Bus
Control
CTS
RTS
RxD
TxD
Control
Logic
or
External Clock (TIN)
Internal Bus
Data
to CPU
IRQ
To Interrupt
Controller
(SIM)
External
Interface
Signals
CLKIN
Clock Source
Generator