Datasheet

About This Book xxxvii

Organization

controller component of the SIM. It begins with a general description and brief

glossary, and includes a description of signals involved in DRAM operations.

The remainder of the chapter is divided between descriptions of asynchronous

and synchronous operations.

• Part III, “Peripheral Module,” describes the operation and conﬁguration of the

MCF5407 DMA, timer, UART, and parallel port modules, and describes how they

interface with the system integration unit, described in Part II.

— Chapter 12, “DMA Controller Module,” provides an overview of the DMA

controller module and describes in detail its signals and registers. The latter

sections of this chapter describe operations, features, and supported data transfer

modes in detail, showing timing diagrams for various operations.

— Chapter 13, “Timer Module,” describes conﬁguration and operation of the two

general-purpose timer modules, timer 0 and timer 1. It includes programming

examples.

— Chapter 14, “UART Modules,” describes the use of the universal

asynchronous/synchronous receiver/transmitters (UARTs) implemented on the

MCF5407 and includes programming examples. Particular attention is given to

the UART1 implementation of a synchronous interface that provides a controller

for an 8- or 16-bit CODEC interface and an audio CODEC ‘97 (AC ’97) digital

interface.

— Chapter 15, “Parallel Port (General-Purpose I/O),” describes the operation and

programming model of the parallel port pin assignment, direction-control, and

data registers. It includes a code example for setting up the parallel port.

• Part IV, “Hardware Interface,” provides a pinout and both electrical and functional

descriptions of the MCF5407 signals. It also describes how these signals interact to

support the variety of bus operations shown in timing diagrams.

— Chapter 16, “Mechanical Data,” provides a functional pin listing and package

diagram for the MCF5407.

— Chapter 17, “Signal Descriptions,” provides an alphabetical listing of MCF5407

signals. This chapter describes the MCF5407 signals. In particular, it shows

which are inputs or outputs, how they are multiplexed, which signals require

pull-up resistors, and the state of each signal at reset.

— Chapter 18, “Bus Operation,” describes data transfers, error conditions, bus

arbitration, and reset operations. It describes transfers initiated by the MCF5407

and by an external bus master, and includes detailed timing diagrams showing

the interaction of signals in supported bus operations. Note that Chapter 11,

“Synchronous/Asynchronous DRAM Controller Module,” describes DRAM

cycles.

— Chapter 19, “IEEE 1149.1 Test Access Port (JTAG),” describes conﬁguration

and operation of the MCF5407 JTAG test implementation. It describes the use of

JTAG instructions and how to disable JTAG functionality.